8
FN4071.12
September 20, 2006
FIGURE 16. TYPICAL MTPR PERFORMANCE
FIGURE 17. SFDR WITHIN A WINDOW
FIGURE 18. TYPICAL SETTLING TIME PERFORMANCE
FIGURE 19. TYPICAL GLITCH ENERGY
Pin Descriptions
PIN NO.
PIN NAME
PIN DESCRIPTION
1-14
D13 (MSB) thru D0 (LSB) Digital Data Bit 13, the Most Significant Bit through Digital Data Bit 0, the Least Significant Bit.
15
CLK
Data Clock Pin 100kHz to 100 MSPS.
16
DVCC
Digital Logic Supply +5V.
17, 28
DGND
Digital Ground.
18
DVEE
-5.2V Logic Supply.
23
RSET
External Resistor to set the full scale output current. IFS = 16 x (VREFOUT/RSET). Typically 976.
27
AGND
Analog Ground Supply current return pin.
19
ARTN
Analog Signal Return for the R/2R ladder.
21
IOUT
Current Output Pin.
20
IOUT
Complementary Current Output pin.
22
AVEE
-5.2V Analog Supply.
24
CTRL AMP IN
Input to the current source base rail. Typically connected to CTRL AMP OUT and a 0.1
F capacitor to AVEE.
Allows external control of the current sources.
25
CTRL AMP OUT
Control amplifier out. Provides precision control of the current sources when connected to CTRL AMP IN
such that IFS = 16 x (VREFOUT/RSET).
26
REF OUT
-1.23V (typical) bandgap reference voltage output. Can sink up to 500
A or be overdriven by an external
reference capable of delivering up to 2mA.
Typical Performance Curves (Continued)
START 1.900MHz
S
STOP 3.100MHz
10dB/
C
fCLK = 20 MSPS
MTPR = 75.17dBc
CENTER 26.637MHz
S
SPAN 2.000MHz
10dB/
C
fCLK = 100 MSPS
fOUT = 26.6MHz
SFDR = 77.5dBc
1
CH1 1.00mV
~
M 5.0ns CH1
-16.9mV
SETTLING TIME
~10ns
: 240V
@: -30.96mV
12-BIT WINDOW
1
CH1 1.00mV
M 5.0ns CH1
-109mV
GLITCH = (0.5) (300
V) (3.3ns)
= 0.495pV/s
: 300V
@: -124.1mV
HI5741
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